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industrial power control final data sheet rev. 2.0, 2012-06-05 2ED020I12-F2 dual igbt driver ic eicedriver?
edition 2012-06-05 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineo n technologies hereby disclaims any and all warranties and liabilities of any kind, including wit hout limitation, warranties of non-infringement of in tellectual property rights of any third party. information for further information on technology , delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contai n dangerous substances. for information on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-s upport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
eicedriver? 2ED020I12-F2 final data sheet 3 rev. 2.0, 2012-06-05 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, ca npak?, cipos?, cipurse?, comn eon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobri dge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfe t?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pr o-sil?, profet?, rasic?, re versave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlew is?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x-go ld?, x-pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2010-10-26 revision history page or item subjects (major changes since previous revision) rev. 2.0, 2012-06-05
eicedriver? 2ED020I12-F2 final data sheet 4 rev. 2.0, 2012-06-05 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 internal protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.1 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.2 ready status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.3 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.4 active shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 non-inverting and inverting inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 external protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6.1 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6.2 active miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6.3 short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 recommended operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.1 voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.2 logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.4 active miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.5 short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.6 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.7 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.8 active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 timing diagramms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents
eicedriver? 2ED020I12-F2 final data sheet 5 rev. 2.0, 2012-06-05 figure 1 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 block diagram 2ED020I12-F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3 pg-dso-36-58 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 application example bipolar supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5 application example unipolar supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6 propagation delay, rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7 typical switching behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8 desat switch-off behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9 uvlo behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10 pg-dso-36-58 (plastic (green) dual small outline package) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 list of figures
eicedriver? 2ED020I12-F2 final data sheet 6 rev. 2.0, 2012-06-05 table 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 absolute maximum ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3 operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4 recommended operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5 voltage supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6 logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8 active miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9 short circuit clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12 active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 list of tables
product name gate drive current package 2ED020I12-F2 2 a pg-dso-36-58 eicedriver? dual igbt driver ic 2ED020I12-F2 final data sheet 7 rev. 2.0, 2012-06-05 1overview main features ? dual channel isolated igbt driver ? for 600v/1200 v igbts ? 2 a rail-to-rail output ? vcesat-detection ? active miller clamp product highlights ? coreless transformer isolated driver ? galvanic insulation ? integrated protection features ? small footprint ? suitable for operation at high ambient temperature typical application ? ac and brushless dc motor drives ? high voltage dc/dc-converter ? ups-systems ? welding description the 2ED020I12-F2 is a galvanic isolated dual channel ig bt driver in pg-dso-36-58 package that provides two fully independent driver ou tputs with a current capability of typically 2a. all logic pins are 5v cmos compatible and coul d be directly connected to a microcontroller. the data transfer across galvanic isolation is realiz ed by the integrated coreless transformer technology. the 2ED020I12-F2 provides several pr otection features like igbt desatura tion protection, active miller clamping and active shut down.
eicedriver? 2ED020I12-F2 overview final data sheet 8 rev. 2.0, 2012-06-05 figure 1 typical application desatls outls cpu inhs+, inhs-, /rsths /flths, rdyhs gnd1 vcc1hs vee2hs gnd2ls vcc1ls inls+, inls-, /rstls /fltls, rdyls vee2ls high side low side vcc2ls clampls desaths ouths gnd2hs vcc2hs clamphs 2 2 2 3 3 3 eicedriver tm 2ED020I12-F2
eicedriver? 2ED020I12-F2 block diagram final data sheet 9 rev. 2.0, 2012-06-05 2 block diagram figure 2 block diagram 2ED020I12-F2 inhs+ inhs- rdyhs /rsths /flths vcc1hs nc 2 3 4 5 6 7 8 9 35 34 33 32 31 30 29 28 ouths vee2hs gnd2hs clamphs vcc2hs not existing desaths & 0 0 0 /rsths logic tx rx logic /flths uvlo tx rx vee2hs vcc2hs logic logic uvlo rdy_loop t t gnd1 1 36 vee2hs inls+ inls- rdyls /rstls /fltls vcc1ls 11 12 13 14 15 16 17 27 26 25 24 23 22 21 20 vee2ls clampls gnd2ls desatls outls & 0 0 0 /rstls logic tx rx logic /fltls uvlo tx rx vee 2ls logic logic i3 desat uvlo rdy_loop t t 9v k3 18 19 vee2ls gnd2ls r vcc2ls 10 nc low side high side gnd1 gnd1 gnd1 not existing not existing not existing vee2ls vcc2ls 2v vee 2hs 2v i3 desat 9v k3 gnd2hs r vcc2hs vcc2ls
eicedriver? 2ED020I12-F2 pin configuration and functionalitypin configuration final data sheet 10 rev. 2.0, 2012-06-05 3 pin configuration and functionality 3.1 pin configuration remark: xxxhs and xxxls at the end of pin name only indi cate an order for description, both drivers are isolated and could be used as high side or low side without any preference. table 1 pin configuration pin no. name function 1 gnd1 common ground input side 2 inhs+ non inverted driver input high side 3 inhs- inverted driver input high side 4 rdyhs ready output high side 5 /flths inverted fault output high side 6 /rsths inverted reset input high side 7 vcc1hs positive power supply input high side 8 gnd1 common ground input side 9 nc not used, internally connected to pin 10 10 nc not used, internally connected to pin 9 11 gnd1 common ground input side 12 inls+ non inverted driver input low side 13 inls- inverted driver input lowside 14 rdyls ready output low side 15 /fltls inverted fault output low side 16 /rstls inverted reset input low side 17 vcc1ls positive power supply input low side 18 gnd1 common ground input side 19 vee2ls negative power su pply low side driver 20 desatls desaturation prot ection low side driver 21 gnd2ls signal ground low side driver 22 vcc2ls power supply low side driver 23 outls output low side driver 24 vee2ls negative power su pply low side driver 25 clampls miller clamping low side driver 26 pin not existing, cut out 27 pin not existing, cut out 28 pin not existing, cut out 29 pin not existing, cut out 30 desaths desaturation prot ection high side driver 31 vee2hs negative power su pply high side driver
eicedriver? 2ED020I12-F2 pin configuration and func tionalitypin functionality final data sheet 11 rev. 2.0, 2012-06-05 figure 3 pg-dso-36-58 (top view) 3.2 pin functionality remark: xxxhs and xxxls at the end of pin name only indi cate an order for description, both drivers are isolated and could be used as high side or low side without any preference. gnd1 common ground connection of the input side. inhs+, inls+ non inverting driver input inxx+ control signal for the driver output if inxx- is set to low (the igbt is on if in xx+ = high and inxx? = low). a minimum pulse width is defined to make the ic robust against glitches at in+. an internal pull-down-resistor ensures igbt off-state. 32 gnd2hs signal ground high side driver 33 vcc2hs power supply high side driver 34 ouths output high side driver 35 clamphs miller clamping high side driver 36 vee2hs negative power su pply high side driver table 1 pin configuration (cont?d) pin no. name function rdyhs /flths inhs+ vcc1hs gnd1 inhs- gnd1 nc /rsths inls+ inls- rdyls /fltls /rstls vcc1ls nc gnd1 gnd1 vee2ls desatls gnd2ls vcc2ls outls vee2ls clampls clamphs desaths vee2hs gnd2hs vcc2hs ouths vee2hs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 25 24 23 22 21 20 19
eicedriver? 2ED020I12-F2 pin configuration and func tionalitypin functionality final data sheet 12 rev. 2.0, 2012-06-05 inhs?, inls? inverting driver input inxx- control signal for driver output if inxx+ is set to high (igbt is on if inxx? = low and inxx+ = high). a minimum pulse width is defined to make the ic robust against glitches at inxx?. an internal pull-up-resistor ensures igbt off-state. /rsths, /rstls reset input function 1: enable/shutdown of the input chip (the igbt is of f if /rstxx = low). a minimum pulse width is defined to make the ic robust ag ainst glitches at /rstxx. function 2: resets the desat-fault-state of the chip if /rstxx is low for a time t rst . an internal pull-up- resistor is used to ensure /fltxx status output. /flths, /fltls fault output open-drain output to report a desaturation error of the igbt (/fltxx is low if desaturation occurs). rdyhs, rdyls ready status output open-drain output to report the correct operation of the device (rdyxx = high if both chips are above the uvlo level and the internal chip transmission is faultless). vcc1hs, vcc1ls positive supply 5 v power supply of the input chip vee2hs, vee2ls negative supply negative power supply pins of the output chip. if no n egative supply voltage is ava ilable, both pins have to be connected to gnd2xx. desaths, desatls desat uration detection input monitoring of the igbt saturation voltage (v ce ) to detect desaturation caused by short circuits. if out is high, v ce is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the igbt is switched off. the blanking time is adjustable by an external capacitor. clamphs, clampls miller clamping ties the gate voltage to ground after the igbt has bee n switched off at a defined voltage to avoid a parasitic switch-on of the igbt.during turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes 2 v below vee2xx. gnd2hs, gnd2ls reference ground reference ground of the output chip. ouths, outls driver output output pin to drive an igbt. the voltage is switch ed between vee2xx and vcc2xx. in normal op erating mode vout is controlled by inxx+, inxx- and /rstxx. during erro r mode (uvlo, internal er ror or desatxx vout is set to vee2xx independent of the input control signals. vcc2hs, vcc2ls positive supply positive power supply pin of the output side.
eicedriver? 2ED020I12-F2 functional descriptionintroduction final data sheet 13 rev. 2.0, 2012-06-05 4 functional description 4.1 introduction the 2ED020I12-F2 is an advanced igbt dual gate driver that can be also used for driving power mos devices. control and protection functions ar e included to make possible the design of high reliability systems. the device consists of two ga lvanic separated driver. the input can be di rectly connected to a standard 5 v dsp or microcontroller with cmos in/output and the output driver are connected to the high side and low side switch. the rail-to-rail driver outputs enables the user to prov ide easy clamping of the igbts gate voltage during short circuit of the igbt. so an increase of short circuit cu rrent due to the feedback via the miller capacitance can be avoided. further, a rail-to-rail ou tput reduces power dissipation. the device also includes ig bt desaturation protection with fault status outputs. two ready status outputs reports if the de vice is supplied and operates correctly. figure 4 application ex ample bipolar supply 4.2 supply the driver 2ED020I12-F2 is designed to support two diff erent supply configurations, bipolar supply and unipolar supply. in bipolar supply the driver is typi cally supplied with a positive voltage of 15v at vcc2 and a negative voltage of -8v at vee2, please refer to figure 4 . negative supply prevents a dynamic tu rn on due to the additional charge which is generated from igbt input capacitance times n egative supply voltage. if an appropriate negative supply voltage is used, connecting clampxx to igbt gate is redundant and therefore typically not necessary. gnd1 inhs+ inhs- rdyhs /flths /rsths vcc1hs ouths vcc2hs gnd2hs clamphs 2ED020I12-F2 desaths +5v vee2hs vcc1ls inls+ inls- rdyls /fltls /rstls sgnd inhs inls rdy flt rs outls vcc2ls gnd2ls clampls desatls vee2ls -8v_1 +15v_1 +15v_2 -8v_2 100nf 100nf 2 * 4k7 10r 10r 1k 1k 1f 1f 1f 1f 220pf 220pf
eicedriver? 2ED020I12-F2 functional descriptioninternal protection features final data sheet 14 rev. 2.0, 2012-06-05 for unipolar supply configuration the driver is typically supplied with a positive voltage of 15v at vcc2. erratically dynamic turn on of the igbt could be prevented with active miller clamp function, so clamp output is directly connected to igbt gate, please refer to figure 5 . figure 5 application exam ple unipolar supply 4.3 internal protection features 4.3.1 undervoltage lockout (uvlo) to ensure correct switching of igbts the device is equipped with undervoltage lockout for all driver outputs as well as for input section, please see figure 9 . if the power supply voltage v vcc1xx of the input section drops below v uvlol1 a turn-off signal is sent to the output driver before power-down. the igbt is switched off and the signals at inxx+ and inxx- are ignored as long as v vcc1xx reaches the power-up voltage v uvloh1 . if the power supply voltage v vcc2xx of the output driver goes down below v uvlol2 the igbt is switched off and signals from the input chip are ignored as long as v vcc2xx reaches the power-up voltage v uvloh2 . vee2xx is not monitored, otherwise negative supply voltage range from 0 v to -12 v would not be possible. 4.3.2 ready status output the ready outputs shows the status of three internal protection features. ? uvlo of the input chip ? uvlo of the output chip after a short delay ? internal signal transmission after a short delay it is not necessary to reset the read y signal since its state only depends on the status of the former mentioned protection signals. gnd1 inhs+ inhs- rdyhs /flths /rsths vcc1hs ouths vcc2hs gnd2hs clamphs 2ED020I12-F2 desaths +5v vee2hs vcc1ls inls+ inls- rdyls /fltls /rstls sgnd inhs inls rdy flt rs outls vcc2ls gnd2ls clampls desatls vee2ls +15v_1 +15v_2 100nf 100nf 2 * 4k7 10r 10r 1k 1k 1f 1f 220pf 220pf
eicedriver? 2ED020I12-F2 functional descriptionnon-inverting and inverting inputs final data sheet 15 rev. 2.0, 2012-06-05 4.3.3 watchdog timer during normal operation the internal signal transmission is monitored by a watchdog time r. if the transmission fails for a given time, the igbt is switched off an d the ready output reports an internal error. 4.3.4 active shut-down the active shut-down feature ensures a safe igbt off-state if the outp ut chip is not connected to the power supply, igbt gate is clam ped at outxx to vee2xx. 4.4 non-inverting and inverting inputs there are two possible input modes to control the igbt. at non-inverting mode inxx+ controls the driver output while inxx- is set to low. at invertin g mode inxx- controls the driver output while inxx+ is set to high, please see figure 7 . a minimum input pulse width is defi ned to filter occasional glitches. 4.5 driver outputs the output driver sections uses only mosfets to provide a rail-to-rail output. this featur e permits that tight control of gate voltage during on-state and sh ort circuit can be maintained as long as the drivers supply is stable. due to the low internal voltage drop , switching behaviour of the igbt is pre dominantly governed by the gate resistor. furthermore, it reduces the power to be dissipated by the driver. 4.6 external protection features 4.6.1 desaturation protection a desaturation protection ensures the protection of the igbt at short circuit. when the desat voltage goes up and reaches 9 v, the output is driven low. further, the fault output is activated, please refer to figure 8 . a programmable blanking time is used to allow enough time for igbt saturation. blanking time is provided by a highly precise internal current source and an external capacitor. 4.6.2 active miller clamp in a half bridge configuration the switched off igbt tends to dynamically turn on during turn on phase of the opposite igbt. a miller clamp allows sinking the miller current across a low impedance path in this high dv/dt situation. therefore in many applications, the us e of a negative supply vo ltage can be avoided. during turn-off, the gate voltage is monitored and the clam p output is activated when the gate voltage goes below typical 2 v (related to vee2). the clamp is designed for a miller current up to 2 a. 4.6.3 short circuit clamping during short circuit the igbts gate vo ltage tends to rise because of the feedback via the miller capacitance. an additional protection circuit connected to outxx and clam pxx limits this voltage to a value slightly higher than the supply voltage. a current of maximum 500 ma for 10 s may be fed back to the supply through one of this paths. if higher currents are expecte d or a tighter clamping is desired external schottky diodes may be added. 4.7 reset the reset inputs ha ve two functions. firstly, /rstxx is in charge of setting back the fault ou tput. if /rstxx is low longe r than a given time, /fltxx will be cleared at the rising edge of /rstxx; otherwise, it will re main unchanged. mor eover, it works as enable/shutdown of the input logic.
eicedriver? 2ED020I12-F2 electrical parametersab solute maximum ratings final data sheet 16 rev. 2.0, 2012-06-05 5 electrical parameters 5.1 absolute maximum ratings note: absolute maximum ratings are defi ned as ratings, which when being exceeded may lead to destruction of the integrated circuit. unless otherwise noted all param eters refer to gnd1. the sp ecification for all driver signals is valid for hs and ls with out special notice, e.g. in+ covers inhs+ as well as inls+. the signals from driver output side are measured with resp ect to their specific gnd2hs or gnd2ls. table 2 absolute maximum ratings parameter symbol values unit note / test condition min. max. positive power supply output side v vcc2 -0.3 20 v 1) negative power supply output side v vee2 -12 0.3 v 1) maximum power supply voltage output side (v vcc2 - v vee2 ) v max2 ?28v? gate driver output v out v vee2 -0.3 v max2 +0.3 v ? gate driver high output maximum current i out ? 2.4 a t = 2 s gate & clamp driver low output maximum current i out ? 2.4 a t = 2 s maximum short circuit clamping time t clp ?10 s i clamp/out = 500 ma positive power supply input side v vcc1 -0.3 6.5 v ? logic input voltages (in+,in-,rst ) v logicin -0.3 6.5 v ? opendrain logic output voltage (flt ) v flt# -0.3 6.5 v ? opendrain logic output voltage (rdy) v rdy -0.3 6.5 v ? opendrain logic output current (flt ) i flt# ?10ma? opendrain logic output current (rdy) i rdy ?10ma? pin desat voltage v desat -0.3 v vcc2 +0.3 v 1) pin clamp voltage v clamp -0.3 v vcc2 +0.3 2) c 3) ? input to output isolation voltage (gnd2) v iso -1200 1200 v output to output isolation voltage (gnd2hs vs gnd2ls) v iso_out -1200 1200 v 1) junction temperature t j -40 150 c ? storage temperature t s -55 150 c ? power dissipation, per input part p d, in ?100mw 4) @ t a = 25c power dissipation, per output part p d, out ?400mw 4) @ t a = 25c power dissipation, total p d, tot ? 1000 mw 4) @ t a = 25c
eicedriver? 2ED020I12-F2 electrical parametersab solute maximum ratings final data sheet 17 rev. 2.0, 2012-06-05 thermal resistance (input part) r thja,in ?375k/w 4) @ t a = 25c, p d, in_hs+ls = 200 mw, p d, out_hs+ls = 800 mw thermal resistance (output part) r thja,out ?110k/w 4) @ t a = 25c, p d, in_hs+ls = 200 mw, p d, out_hs+ls = 800 mw esd capability v esd ? 1 kv human body model 5) 1) with respect to gnd2. 2) may be exceeded during short circuit clamping. 3) with respect to vee2. 4) ic power dissipation is derated linearly at 11.8 mw/c ab ove 65c. thermal performance ma y change significantly with layout and heat dissipation of components in close proximity. 5) according to eia/jesd22-a114-b (discharging a 100 pf capacitor through a 1.5 k ? series resistor). table 2 absolute maximum ratings (cont?d) parameter symbol values unit note / test condition min. max.
eicedriver? 2ED020I12-F2 electrical parameters operating parameters final data sheet 18 rev. 2.0, 2012-06-05 5.2 operating parameters note: within the operating range the ic operates as de scribed in the functional description. unless otherwise noted all parameters refer to gnd1. the specification fo r all driver signals is valid for hs and ls with out special notic, e.g. in+ covers inhs+ as well as inls +. the signals from driver output side are measured with respect to their specific gnd2hs or gnd2ls. 5.3 recommended operating parameters note: unless otherwise noted all parameters refer to gnd1. the specification for all driv er signals is valid for hs and ls with out special notic, e.g. in+ covers inhs+ as well as inls+. the signals from driver output side are measured with respect to their specific gnd2hs or gnd2ls. table 3 operating parameters parameter symbol values unit note / test condition min. max. positive power supply output side v vcc2 13 20 v 1) 1) with respect to gnd2. negative power supply output side v vee2 -12 0 v 1) maximum power supply voltage output side ( v vcc2 - v vee2 ) v max2 ?28v? positive power supply input side v vcc1 4.5 5.5 v ? logic input voltages (in+,in-,rst) v logicin -0.3 5.5 v ? pin clamp voltage v clamp v vee2 -0.3 v vcc2 2) 2) may be exceeded during short circuit clamping. v? pin desat voltage v desat -0.3 v vcc2 v 1) pin tlset voltage v tlset -0.3 v vcc2 v 1) ambient temperature t a -40 125 c ? common mode transient immunity 3) 3) the parameter is not subject to production test - verified by design/characterization |d v iso /dt| ? 50 kv/ s@ 500v table 4 recommended operating parameters parameter symbol value unit note / test condition positive power supply output side v vcc2 15 v 1) 1) with respect to gnd2. negative power supply output side v vee2 -8 v 1) positive power supply input side v vcc1 5v?
eicedriver? 2ED020I12-F2 electrical parameterselectrical characteristics final data sheet 19 rev. 2.0, 2012-06-05 5.4 electrical characteristics note: the electrical characteristics involve the spread of values for the supply voltages, load and junction temperatures given below. typical values represent th e median values, which are related to production processes at t = 25c. unless otherwise noted all voltag es are given with respect to gnd. the specification for all driver signals is valid for hs and ls with out special notic, e.g. in+ covers inhs+ as well as inls+. the signals from driver output side are measured wit h respect to their specific gnd2hs or gnd2ls. 5.4.1 voltage supply table 5 voltage supply parameter symbol values unit note / test condition min. typ. max. uvlo threshold input chip v uvloh1 ?4.14.3v? v uvloh1 3.5 3.8 ? v ? uvlo hysteresis input chip ( v uvloh1 - v uvlol1 ) v hys1 0.15 ? ? v ? uvlo threshold output chip v uvloh2 ?12.012.6v? v uvlol2 10.4 11.0 ? v ? uvlo hysteresis output chip ( v uvloh1 - v uvlol1 ) v hys2 0.7 0.9 ? v ? quiescent current input chip i q1 ?79ma v vcc1 = 5 v in+ = high, in- = low =>out = high, rdy = high, /flt = high quiescent current output chip i q2 ?46ma v vcc2 = 15 v v vee2 = -8 v in+ = high, in- = low =>out = high, rdy = high, /flt = high
eicedriver? 2ED020I12-F2 electrical parameterselectrical characteristics final data sheet 20 rev. 2.0, 2012-06-05 5.4.2 logic input and output table 6 logic input and output parameter symbol values unit note / test condition min. typ. max. in+,in-, rst low input voltage v in+l , v in-l , v rstl# ??1.5v? in+,in-, rst high input voltage v in+h , v in-h , v rsth# 3.5??v? in-, rst input current i in- , i rst# -400 -100 ? a v in- = gnd1 v rst# = gnd1 in+ input current i in+ , ? 100 400 a v in+ = vcc1 rdy,flt pull up current i prdy , i pflt# -400 -100 ? a v rdy = gnd1 v flt# = gnd1 input pulse suppression in+, in- t minin+ , t minin- 30 40 ? ns ? input pulse suppression rst for enable/shutdown t minrst 30 40 ? ns ? pulse width rst for reseting flt t rst 800??ns? flt low voltage v fltl ??300mv i sink(flt#) = 5 ma rdy low voltage v rdyl ??300mv i sink(rdy) = 5 ma
eicedriver? 2ED020I12-F2 electrical parameterselectrical characteristics final data sheet 21 rev. 2.0, 2012-06-05 5.4.3 gate driver 5.4.4 active miller clamp table 7 gate driver parameter symbol values unit note / test condition min. typ. max. high level output voltage v outh1 v cc2 -1.2 v cc2 -0.8 ? v i outh = -20 ma v outh2 v cc2 -2.5 v cc2 -2.0 ? v i outh = -200 ma v outh3 v cc2 -9 v cc2 -5 ? v i outh = -1 a v outh4 v cc2 -10 ? v i outh = -2 a high level output peak current i outh -1.5 -2.0 ? a in+ = high, in- = low; out = high low level output voltage v outl1 ? v vee2 +0.04 v vee2 +0.09 v i outl = 20 ma v outl2 ? v vee2 +0.3 v vee2 +0.85 v i outl = 200 ma v outl3 ? v vee2 +2.1 v vee2 +5 v i outl = 1 a v outl4 ? v vee2 +7 ? v i outl = 2 a low level output peak current i outl 1.5 2.0 ? a in+ = low, in- = low; out = low, v vcc2 = 15 v, v vee2 = -8 v table 8 active miller clamp parameter symbol values unit note / test condition min. typ. max. low level clamp voltage v clampl1 ? v vee2 +0.03 v vee2 +0.08 v i outl = 20 ma v clampl2 ? v vee2 +0.3 v vee2 +0.8 v i outl = 200 ma v clampl3 ? v vee2 +1.9 v vee2 +4.8 v i outl = 1 a low level clamp current i clampl 2??a 1) 1) the parameter is not subject to production test - verified by design/characterization clamp threshold voltage v clamp 1.6 2.1 2.4 v related to vee2
eicedriver? 2ED020I12-F2 electrical parameterselectrical characteristics final data sheet 22 rev. 2.0, 2012-06-05 5.4.5 short circuit clamping 5.4.6 dynamic characteristics dynamic characteristics are measured with v vcc1 = 5 v, v vcc2 = 15 v and v vee2 = -8 v. table 9 short circuit clamping parameter symbol values unit note / test condition min. typ. max. clamping voltage (out) ( v out - v vcc2 ) v clpout ? 0.8 1.3 v in+ = high, in- = low, out = high i out = 500 ma pulse test, t clpmax = 10 s) clamping voltage (clamp) ( v vclamp - v vcc2 ) v clpclamp ? 1.3 ? v in+ = high, in- = low, out = high i clamp = 500 ma (pulse test, t clpmax = 10 s) clamping voltage (clamp) v clpclamp ? 0.7 1.1 v in+ = high, in- = low, out = high i clamp = 20 ma table 10 dynamic characteristics parameter symbol va lues unit note / test condition min. typ. max. in+, in- input to output propa-gation delay on t pdon 145 170 195 ns c load = 100 pf v in+ = 50%, v out =50% @ 25c in+, in- input to output propa-gation delay off t pdoff 145 165 190 ns in+, in- input to output propa-gation delay distortion ( t pdoff - t pdon ) t pdisto -35 -5 25 ns in+, in- input to output propagation delay on variation due to temp t pdont ??25ns 1) c load = 100 pf v in+ = 50%, v out =50% in+, in- input to output propagation delay off variation due to temp t pdofft ??40ns 1) c load = 100 pf vin+ = 50%, vout=50% in+, in- input to output propagation delay distortion variation due to temp ( t pdoff - t pdon ) t pdistot ??20ns 1) c load = 100 pf vin+ = 50%, vout=50%
eicedriver? 2ED020I12-F2 electrical parameterselectrical characteristics final data sheet 23 rev. 2.0, 2012-06-05 5.4.7 desaturation protection rise time t rise 10 30 60 ns c load = 1 nf v l 10%, v h 90% 200 400 800 ns c load = 34 nf v l 10%, v h 90% fall time t fall 10 50 90 ns c load = 1 nf v l 10%, v h 90% 200 350 600 ns c load = 34 nf v l 10%, v h 90% 1) the parameter is not subject to production test - verified by design/characterization table 11 desaturation protection parameter symbol values unit note / test condition min. typ. max. blanking capacitor charge current i desatc 450 500 550 a v vcc2 =15 v, v vee2 =- 8 v v desat = 2 v blanking capacitor discharge current i desatd 914?ma v vcc2 =15 v, v vee2 = -8 v v desat = 6 v desaturation reference level v desat 8.39 9.5v v vcc2 = 15 v desaturation filter time t desatfilter ?250?ns v vcc2 = 15 v, v vee2 = -8 v v desat = 9 v desaturation sense to out low delay t desatout ? 350 430 ns v out = 90% c load = 1 nf desaturation sense to flt low delay t desatflt ??2.25 s v flt# = 10%; i flt # = 5 ma desaturation low voltage v desatl 0.4 0.6 0.95 v in+ = low, in- = low, out = low leading edge blanking t desatleb ? 400 ? ns not subject of production test table 10 dynamic characteristics (cont?d) parameter symbol va lues unit note / test condition min. typ. max.
eicedriver? 2ED020I12-F2 electrical parameterselectrical characteristics final data sheet 24 rev. 2.0, 2012-06-05 5.4.8 active shut down table 12 active shut down parameter symbol values unit note / test condition min. typ. max. active shut down voltage v actsd 1) 1) with refe rence to vee2 ??2.0v i out = -200 ma, v cc2 open
eicedriver? 2ED020I12-F2 timing diagrammselectric al characteristics final data sheet 25 rev. 2.0, 2012-06-05 6timing diagramms figure 6 propagation delay, rise and fall time figure 7 typical switching behavior in+ out t pd on 50 % 50 % t pd off 10 % 90 % t rise t fall out /rst in+ in-
eicedriver? 2ED020I12-F2 timing diagrammselectric al characteristics final data sheet 26 rev. 2.0, 2012-06-05 figure 8 desat switch-off behavior figure 9 uvlo behavior v desat typ. 9v >t rstmin out desat in+ /flt /rst t pd on t desatflt t desatout t d esatfilter t desatleb t pd on t desatleb t pd off blanking tim e out /rst in+ vcc2 vcc1 rdy /flt esd diode conduction v uvloh2 v uvlol2 v uvloh1 v uvlol1
eicedriver? 2ED020I12-F2 package outlineselectrical characteristics final data sheet 27 rev. 2.0, 2012-06-05 7 package outlines figure 10 pg-dso-36-58 (plastic (green) dual small outline package) 0.504 0.104 0.016 0.013 0.417 0.299 0.035 0.018 millimeters l t1 h ccc f3 f2 f1 ddd d dim a2 a b c e e1 n e - min 32 0.020 0.004 0.007 0.010 0 8 2.45 max inches 32 0.026 bsc 0.496 min - 0.089 0.010 0.009 0.394 0.291 max 0.096 scale 1.0 0 2mm 0 1.0 2.25 2.65 0.41 0.32 12.80 10.60 7.60 7.40 10.00 12.60 0.23 0.25 0.90 0.50 0.45 0.25 8 0 0.17 0.10 0.65 bsc 02 issue date 25.03.2011 document no. z8b00159298 european projection revision 9.73 0.45 1.67 0.383 0.018 0.066 footprint a1 0.20 0.004 0.008 0.10 0 8 8 0 t
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